Description: 全数字锁相环的verilog源代码，包括鉴相器，K变摸可逆计数器，加减脉冲器和N分频器。已经仿真实现。(All digital phase-locked loop Verilog source code, including phase discriminator, K variable touch reversible counter, add and subtract pulse and N frequency divider. Have been implemented by simulation.) Platform: |
Size: 11264 |
Author:小米1
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Description: FPGA上机文件一所以在FPGA中采用同 步设计非常重要 MAX+PLUS II可以计算出数据传输需要(fpga Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency) Platform: |
Size: 33792 |
Author:coldplay
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Description: 分频器分频为2Hz后，使计数时间变为0.5秒一个，将此时的频率传给计数器，计数器计数的变化时间就变为0.5秒一变然后再用数码管显示出数字的变化，即可得到一个从0~9变化的计时器。
文件名为随便起的项目名称，使用时如果更改需要和代码中的实体名等一起更改(Frequency divider for 2Hz, the counting time is 0.5 seconds a, the frequency to change the time counter counter becomes 0.5 seconds for a variable and then use the digital display changes, you can get a change from the 0~9 timer.
The file name is the name of the item that you want to change when used, and the changes need to be changed together with the entity name in the code) Platform: |
Size: 193536 |
Author:关关关
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Description: 2、 掌握QuartusII软件的使用；
3、 掌握计数器的设计；
4、 掌握分频器的设计；
5、 掌握时、分、秒的设计；
6、 数码管的扫描显示；
7、 掌握数字钟的整体设计(2, master the use of QuartusII software;
3. Master the design of the counter;
4. Master the design of frequency divider;
5, mastering the design of time, time and time.
6, the scanning display of the digital tube;
7. Master the overall design of the digital clock) Platform: |
Size: 2040832 |
Author:夜光
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Description: 采用定时器/计数器T0对外部脉冲进行计数，每计数100个脉冲后，T0转为定时工作方式。定时1ms后，又转为计数方式，如此循环不止。假定MCS-51单片机的晶体振荡器的频率为6MHz，请使用方式1实现(A timer / counter T0 is used to count the external pulse. After counting 100 pulses, T0 turns to a timing operation. After timing 1ms, it turns to count mode, so the cycle is more than one. Suppose the frequency of the crystal oscillator of MCS-51 single chip is 6MHz, please use mode 1) Platform: |
Size: 10240 |
Author:枫叶。。 |
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Description: WirelessNetView is a small utility that runs in the background, and
monitor the activity of wireless networks around you. For each detected
network, it displays the following information: SSID, Last Signal
Quality, Average Signal Quality, Detection Counter, Authentication
Algorithm, Cipher Algorithm, MAC Address, RSSI, Channel Frequency,
Channel Number, and more. Platform: |
Size: 1024 |
Author:Mariofer |
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Description: VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，同步计数器，序列检测器的设计，序列信号发生器，一般状态机等等。(The small program of some textbooks. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 priority encoder, 8 choose 1, BCD-7 segment display decoder truth table, half adder, Moore state machine, digital frequency meter, digital clock, synchronous counter, sequence detector design. Sequence signal generator, general state machine etc..) Platform: |
Size: 40960 |
Author:girl_lily |
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Description: FPGA设计中，实现基准时钟的分频模块，该模块是将外围电路中所提供的50MHZ将其分频，对时钟模块作用后产生一秒一秒的时钟信号，另外对显示模块的计数器提供时钟实现显示模块的扫描功能。(The design of FPGA, the reference clock frequency module, this module is provided in the peripheral circuit of the 50MHZ frequency, the clock module generates a clock signal after a second second, also provides the clock display function module display module to scan the counter.) Platform: |
Size: 6310912 |
Author:i belive |
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Description: 一种设计数字锁相环的思路，包含异或鉴相器、k模可逆计数器、脉冲加减计数器、N分频器等，实现相位的锁定。(A design of digital phase locked loop (PLL) consists of a phase discriminator, a K mode reversible counter, a pulse addition and subtraction counter, a N frequency divider and so on, to lock the phase.) Platform: |
Size: 1024 |
Author:和风5254 |
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Description: 在ise软件上，用VHDL语言，设计的数字跑表，可以两位计数，含分频器，计数器(In the ISE software, using VHDL language digital stopwatch design, can two counts, including frequency divider, counter) Platform: |
Size: 762880 |
Author:uestczzz |
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Description: EDA仿真工具使用的，进行EDA开发的多个程序；
包括：4位全加器，12分频，128分频，篮球计数秒表（部分），计数器；
可以搭配EDA仿真软件使用，也可以搭配开发板使用；(EDA simulation tools used for EDA development of multiple programs;
Including: 4 bit full adder, 12 frequency division, 128 frequency division, basketball counting stopwatch (part), counter;
It can be used with EDA simulation software or with development board.) Platform: |
Size: 1024 |
Author:李云龙777 |
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Description: 将一个1Mhz的信号分频成100khz、10khz、1khz、100hz。实验要求每相差十倍频率就有脉冲输出，推荐采用十进制计数器对信号进行分频，即判断输入信号上升沿或下降沿的个数，每计满5个即让输出信号电平翻转，以此实现10分频。(Divide a 1Mhz signal into 100kHz, 10kHz, 1kHz and 100Hz. The experiment requires that every ten times the frequency of the difference is pulse output, it is recommended to use decimal counter to divide the signal, that is to judge the number of the rising or descending edge of the input signal, which is full 5, so that the output signal level is turned over, so as to achieve 10 frequency division.) Platform: |
Size: 1024 |
Author:233eeee |
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Description: LS7366，光栅尺计数器，四倍频，所有情况都写进去了，已调通(LS7366, grating scale counter, four times frequency, all cases are written in, and have been switched on.) Platform: |
Size: 6793216 |
Author:aishouyu |
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Description: 使用vhdl语言原件例化设计数字频率计，并用6位7段数码管计数。模块包括：十进制计数器，6位10进制计数器，Reg24 锁存器、Fp 分频器、Ctrl 频率控制器、Disp 动态显示。(The digital frequency meter is designed by using VHDL language as an example and counted by 6-bit 7-segment digital tube. Modules include: decimal counter, 6-bit decimal counter, Reg24 latch, Fp frequency divider, Ctrl frequency controller, Disp dynamic display.) Platform: |
Size: 11264 |
Author:贵阳余文乐 |
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Search - frequency counter